The present invention relates to a clock synchronizing circuit that may be used when lowering a clock signal's frequency in order to reduce power dissipation in a graphics processor integrated circuit.
It is often desirable to decrease the power dissipation in integrated circuits. A reduction in power dissipation lengthens the life of an integrated circuit, simplifies or eliminates components used for cooling such as fans and heat sinks, and simplifies board and system level power distribution.
In CMOS circuits, where there are few, if any, static bias sources, power dissipation is primarily due to voltage changes of transient signals. As a node in an integrated circuit changes in voltage, capacitance at that node is either charged or discharged. This charging and discharging translates into supply current, which results in integrated circuit power dissipation. As the frequency of these transient signals increase, the charging and discharging currents occur more frequently, and power dissipation increases.
A primary source of voltage transients in many integrated circuits is clock signals. For example, it has been found that for many graphics processors, the primary sources of power dissipation are clock signals in general, and memory clock signals in particular. The memory clock is typically responsible for clocking circuits that store and retrieve data to and from an external memory, and for providing data to one or more display heads. But the memory clock is also provided to a delay-locked loop (DLL) in the external memory, and these DLLs tend to lose lock if the memory clock's frequency changes.
Thus, it is desirable to save power by reducing a memory clock's frequency when its associated circuitry is either idle or can process data at a slower rate. It is also preferable to do this while maintaining the frequency of the memory clock provided to the external memory.